IEEE DTTIS’23 Special Sessions
Special Session 1
Dear colleagues,
We would like to invite you to submit your paper for DTTIS conference within the special session
New trends on embedded systems: special focus on the emerging applications Artificial Intelligence AI and blockchain
Description:
Embedded systems are a category of electronic systems dedicated for a specific task or domain. They are used in various domains such as consumer electronics, automobiles, medical devices, mobile robots and industrial automation. With the rapid emergence of complex applications such as artificial intelligence (AI) and blockchains techniques, the integration of these advanced algorithms into embedded systems has become increasingly important and challenging. Indeed, as these applications are both data and computing intensive, their execution on relatively low complex architecture puts stringent constrains on both applications and architectures.
The scope of this special issue includes, but is not limited to the following topics:
- FPGA-based AI accelerators
- AI applications for mobile robots
- Cases study of Edge AI GPU Computing
- Blockchain architectures with embedded systems
- Blockchain applications for embedded systems
- Blockchain consensus HW implementation
- Lightweight Blockchain implementation
- AI-based Hardware reliability
Presenter: Full name: Fakhreddine GHAFFARI |
Presenters Biography:
Nader Ben Amor is an associate professor at the National Engineering School of Sfax, Tunisia. He received his PhD in Electrical Engineering from both Sfax University (Tunisia) and Bretagne Sud University (France) in 2005. His research interests are Hardware-Software System on Chip, self adaptive systems, real time image processing on FPGA systems, robotics, embedded IA systems. |
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Tarek Frikha was born in Sfax (Tunisia) in 1982; He is an assistant professor in National Engineering School of Sfax. He received the engineer degree in electronic engineering from National School of Engineers of Sfax, in 2006 and the Master Diploma from polytech Sophia Antipolis in France. He received a Ph.D. in PhD in science and technology of information and communication in University of South Brittany, France, and the National Engineering School of Sfax, Tunisia. His research interests include Multiprocessor architecture optimization for multimedia domains and hardware/software codesign, approximate computing, Blockchain for multimedia applications, medical and paramedical data and agricultural applications. |
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Jalel ktari is an assistant professor in National Engineering School of Sfax. He received his Diploma in Electrical Engineering and his M.S. From Electrical and Computer Engineering from the National Engineering School of Sfax, Tunisia, in 2003 and 2005, respectively. He received his Ph.D. degree in Computer Engineering in 2009 at National Engineering School of Sfax in Tunisia. His current research interests include Hardware-Software System on Chip, He completed his HDR in the low power embedded blockchain. |
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Fakhreddine Ghaffari (Member, IEEE) received the degree in electrical engineering and master’s degree from the National School of Electrical Engineering (ENIS), Tunisia, in 2001 and 2002, respectively, and the Ph.D. degree in electronics and electrical engineering from the University of Sophia Antipolis, France, in 2006. He is currently an Associate Professor with CY Cergy Paris University, France. His research interests include VLSI design and implementation of reliable digital architectures for wireless communication applications in ASIC/FPGA platform and the study of mitigating transient faults from algorithmic and implementation perspectives for high-throughput applications. |
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Important dates:
Paper Submission deadline: september 20, 2023
Authors Notification: October 1, 2023
Camera Ready and Registration: October 7, 2023
Conference date: November 1-4, 2023
Participation: Participation to this special session will be via easychair. For more details, you can visit the conference website https://www.dttis.org/
The online submission is available through the EasyChair System.
For papers submission, please use the active link below :
Special Session 2
Chiplet Heterogeneous Integration Technology: Status and Challenges
Abstract:
As a heterogeneous integration technology, the chiplet-based design technology integrates multiple heterogeneous dies of diverse functional circuit blocks into a single chip by using advanced packaging technology, which is a promising way to tackle limitation of Moore’s law scaling. As the costs skyrocket for advanced nodes, packaging is becoming an enabler, a viable option and a differentiator, the next dimension in technology scaling became 2.5D and 3D heterogeneous integration. Instead of cramming everything on a large die, the idea is to break up the die into smaller dies and integrate them in a package. Chiplets allows IC designers to merge dies fabricated at different process nodes and reuse them in different projects, which helps to reduce the cost during design and improve yield. Chiplets are poised to become “the new normal”, chip industry is making good progress on standardizing the infrastructure for chiplets, setting the stage for faster and more predictable integration of different functions and features from different vendors.
In this session, we look back at the industry’s efforts over the past decade and summary the concepts and techniques associated with chiplets. In the end, a discussion and conclusion will be given to forecast the future of chiplets.
Keywords:
chip integration; chip package; heterogeneous, Chiplet
Session Topics:
Industry Scale Reuse in the Chiplet Era: The emergence of 2.5D heterogeneous die integration using a silicon (or organic) interposer has enabled unique system architectures. The term “More than Moore” has been used to describe the circuit density and cost advantages of leveraging multiple die in the package, the die potentially in different process technologies.
Die to Die interconnect: Universal Chiplet Interconnect Express (UCIe): The efforts to develop “standard” (short-reach and ultra-short-reach) communication interfaces between the heterogeneous die will further promote integration efforts through die re-use. The UCIe™ Consortium and other important chiplet-related industry collaboration efforts are key to more comprehensive reuse at industry scale, fundamentally reshaping how our industry collaborates to build future systems.
EDA flow for 2.5D and 3D Die Integration: The EDA tool/platform development required to enable advanced 2.5D & 3D integration leveraging multi-die packages (on organic substrates)
Testability for 2.5D and 3D Die Integration: Test is key, in a heterogenous integrated system, the impact of composite yield fallout due to a single chiplet is creating new performance imperatives for wafer test in terms of test complexity and coverage. From a test perspective, making chiplets a mainstream technology depends on ensuring Know Good Dies (KGD) at a reasonable test cost.
| Presenter: Full name: Salem Abdennadher Affiliation: Intel Corporation Email: salem.abdennadher@intel.com |
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Presenter Biography:
Salem Abdennadher, Principal Engineer, Intel Corporation has 20+ years of experience in mixed-signal design and DFT. Soon after graduating with Masters from Oregon State University 1992, he joined the industry and has worked with a research lab in Tunisia, Motorola, Level One Communications and Intel. His recent publications and international patent filing in mixed signal DFT/BIST ranges from Filter BIST, On-chip Jitter BIST, to mixed signal behavioral modeling and noise extraction and prediction. Salem also has presented dozens of tutorials through TTEP at ATS, LATW, VTS, ITC. Presented multiple Workshops, publication, Special sessions presentation in International test Conference, VLSI test Symposium. European Test Symposium, Latin test Workshop
