IEEE DTTIS’23 Invited Papers
Invited Paper 1
Presentation subject: Advanced IC packaging in the context of multi-chiplet based architectures.
Presenter: Full name: Syhem Larguech Affiliation:Application Engineer at Cadence Design Systems, München, Bayern, Deutschland. Email: syheml@cadence.com |
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Summary:
The semiconductor industry is moving from monolithic chips to the world of 3D-IC, chiplets and stacked silicon and wafers. Advanced systems-on-chip (SoCs) are reaching reticle size limits, and as many companies now realize, simply following Moore’s Law alone (More Moore) is no longer the best technical and economical path forward for the next wave of designs. As we approach the device scaling limitations at advanced nodes, the demand on compute performance and data transfer is at an all-time high. There has been a need to find innovative solutions to continue Moore’s law scaling and achieve performance improvements with reduced power.
The semiconductor packaging industry is now poised to take on a larger, more significant role in electronic product design of the future. Stacking chips in the same package (3D) and a multi-chiplet system with silicon interposer on the same package (2.5D) are emerging as solutions of choice, which come with their own challenges.
To meet the market demand of the heterogenous chiplet-based architectures, new system level design methodologies are required, targeting system-level Power, Performance and Area (PPA). The Cadence Integrity 3D-IC platform is the industry’s first integrated solution for system planning, implementation, and accurate early analysis. It leverages Cadence’s industry-leading implementation and signoff technologies for digital, analog, and packaging through a unified hierarchical database.
